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## 

##  Xilinx, Inc. 2010            www.xilinx.com 

##  Thu Dec 12 10:29:14 2019


##  Generated by MIG Version 4.2

##  

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##  File name :       main_mig_7series_0_0.xdc

##  Details :     Constraints file

##                    FPGA Family:       SPARTAN7

##                    FPGA Part:         XC7S50-CSGA324

##                    Speedgrade:        -1

##                    Design Entry:      VERILOG

##                    Frequency:         333.32999999999998 MHz

##                    Time Period:       3000 ps

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## Controller 0

## Memory Device: DDR3_SDRAM->Components->MT41J512M8XX-125

## Data Width: 8

## Time Period: 3000

## Data Mask: 1

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set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ]

set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ]

          

#create_clock -period 2.5 [get_ports sys_clk_i]

          

#create_clock -period 5 [get_ports clk_ref_i]

          

############## NET - IOSTANDARD ##################





# PadFunction: IO_L22N_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[0]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]

set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[0]}]



# PadFunction: IO_L22P_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[1]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]

set_property PACKAGE_PIN H5 [get_ports {ddr3_dq[1]}]



# PadFunction: IO_L24P_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[2]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]

set_property PACKAGE_PIN H6 [get_ports {ddr3_dq[2]}]



# PadFunction: IO_L20N_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[3]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]

set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[3]}]



# PadFunction: IO_L20P_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[4]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]

set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[4]}]



# PadFunction: IO_L23N_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[5]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]

set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[5]}]



# PadFunction: IO_L24N_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[6]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]

set_property PACKAGE_PIN G6 [get_ports {ddr3_dq[6]}]



# PadFunction: IO_L23P_T3_35 

set_property SLEW FAST [get_ports {ddr3_dq[7]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]

set_property PACKAGE_PIN J2 [get_ports {ddr3_dq[7]}]



# PadFunction: IO_L1N_T0_AD4N_35 

set_property SLEW FAST [get_ports {ddr3_addr[15]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[15]}]

set_property PACKAGE_PIN A7 [get_ports {ddr3_addr[15]}]



# PadFunction: IO_L1P_T0_AD4P_35 

set_property SLEW FAST [get_ports {ddr3_addr[14]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]

set_property PACKAGE_PIN A8 [get_ports {ddr3_addr[14]}]



# PadFunction: IO_L4N_T0_35 

set_property SLEW FAST [get_ports {ddr3_addr[13]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]

set_property PACKAGE_PIN A6 [get_ports {ddr3_addr[13]}]



# PadFunction: IO_L8N_T1_AD14N_35 

set_property SLEW FAST [get_ports {ddr3_addr[12]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]

set_property PACKAGE_PIN B3 [get_ports {ddr3_addr[12]}]



# PadFunction: IO_L10P_T1_AD15P_35 

set_property SLEW FAST [get_ports {ddr3_addr[11]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]

set_property PACKAGE_PIN A3 [get_ports {ddr3_addr[11]}]



# PadFunction: IO_L7P_T1_AD6P_35 

set_property SLEW FAST [get_ports {ddr3_addr[10]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]

set_property PACKAGE_PIN C4 [get_ports {ddr3_addr[10]}]



# PadFunction: IO_L15N_T2_DQS_35 

set_property SLEW FAST [get_ports {ddr3_addr[9]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]

set_property PACKAGE_PIN E3 [get_ports {ddr3_addr[9]}]



# PadFunction: IO_L4P_T0_35 

set_property SLEW FAST [get_ports {ddr3_addr[8]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]

set_property PACKAGE_PIN B7 [get_ports {ddr3_addr[8]}]



# PadFunction: IO_L13P_T2_MRCC_35 

set_property SLEW FAST [get_ports {ddr3_addr[7]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]

set_property PACKAGE_PIN F4 [get_ports {ddr3_addr[7]}]



# PadFunction: IO_L5N_T0_AD13N_35 

set_property SLEW FAST [get_ports {ddr3_addr[6]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]

set_property PACKAGE_PIN D6 [get_ports {ddr3_addr[6]}]



# PadFunction: IO_L10N_T1_AD15N_35 

set_property SLEW FAST [get_ports {ddr3_addr[5]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]

set_property PACKAGE_PIN A2 [get_ports {ddr3_addr[5]}]



# PadFunction: IO_L9N_T1_DQS_AD7N_35 

set_property SLEW FAST [get_ports {ddr3_addr[4]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]

set_property PACKAGE_PIN A4 [get_ports {ddr3_addr[4]}]



# PadFunction: IO_L12N_T1_MRCC_35 

set_property SLEW FAST [get_ports {ddr3_addr[3]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]

set_property PACKAGE_PIN B1 [get_ports {ddr3_addr[3]}]



# PadFunction: IO_L12P_T1_MRCC_35 

set_property SLEW FAST [get_ports {ddr3_addr[2]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]

set_property PACKAGE_PIN C1 [get_ports {ddr3_addr[2]}]



# PadFunction: IO_L7N_T1_AD6N_35 

set_property SLEW FAST [get_ports {ddr3_addr[1]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]

set_property PACKAGE_PIN B4 [get_ports {ddr3_addr[1]}]



# PadFunction: IO_L14N_T2_SRCC_35 

set_property SLEW FAST [get_ports {ddr3_addr[0]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]

set_property PACKAGE_PIN D1 [get_ports {ddr3_addr[0]}]



# PadFunction: IO_L16N_T2_35 

set_property SLEW FAST [get_ports {ddr3_ba[2]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]

set_property PACKAGE_PIN D2 [get_ports {ddr3_ba[2]}]



# PadFunction: IO_L5P_T0_AD13P_35 

set_property SLEW FAST [get_ports {ddr3_ba[1]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]

set_property PACKAGE_PIN E6 [get_ports {ddr3_ba[1]}]



# PadFunction: IO_L11N_T1_SRCC_35 

set_property SLEW FAST [get_ports {ddr3_ba[0]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]

set_property PACKAGE_PIN B2 [get_ports {ddr3_ba[0]}]



# PadFunction: IO_L18P_T2_35 

set_property SLEW FAST [get_ports {ddr3_ras_n}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]

set_property PACKAGE_PIN F2 [get_ports {ddr3_ras_n}]



# PadFunction: IO_L18N_T2_35 

set_property SLEW FAST [get_ports {ddr3_cas_n}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]

set_property PACKAGE_PIN F1 [get_ports {ddr3_cas_n}]



# PadFunction: IO_L16P_T2_35 

set_property SLEW FAST [get_ports {ddr3_we_n}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]

set_property PACKAGE_PIN E2 [get_ports {ddr3_we_n}]



# PadFunction: IO_L15P_T2_DQS_35 

set_property SLEW FAST [get_ports {ddr3_reset_n}]

set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]

set_property PACKAGE_PIN F3 [get_ports {ddr3_reset_n}]



# PadFunction: IO_L8P_T1_AD14P_35 

set_property SLEW FAST [get_ports {ddr3_cke[0]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]

set_property PACKAGE_PIN C3 [get_ports {ddr3_cke[0]}]



# PadFunction: IO_L14P_T2_SRCC_35 

set_property SLEW FAST [get_ports {ddr3_odt[0]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]

set_property PACKAGE_PIN E1 [get_ports {ddr3_odt[0]}]



# PadFunction: IO_L11P_T1_SRCC_35 

set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]

set_property PACKAGE_PIN C2 [get_ports {ddr3_cs_n[0]}]



# PadFunction: IO_L19P_T3_35 

set_property SLEW FAST [get_ports {ddr3_dm[0]}]

set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]

set_property PACKAGE_PIN J4 [get_ports {ddr3_dm[0]}]



# PadFunction: IO_L21P_T3_DQS_35 

set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]

set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]

set_property PACKAGE_PIN G2 [get_ports {ddr3_dqs_p[0]}]



# PadFunction: IO_L21N_T3_DQS_35 

set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]

set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]

set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]

set_property PACKAGE_PIN G1 [get_ports {ddr3_dqs_n[0]}]



# PadFunction: IO_L3P_T0_DQS_AD5P_35 

set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]

set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]

set_property PACKAGE_PIN D7 [get_ports {ddr3_ck_p[0]}]



# PadFunction: IO_L3N_T0_DQS_AD5N_35 

set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]

set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]

set_property PACKAGE_PIN C7 [get_ports {ddr3_ck_n[0]}]









set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]

set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]

set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]

set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]





## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]

## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]

## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]

set_property LOC PHASER_IN_PHY_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]











set_property LOC OUT_FIFO_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]

set_property LOC OUT_FIFO_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]

set_property LOC OUT_FIFO_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]

set_property LOC OUT_FIFO_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]





set_property LOC IN_FIFO_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]





set_property LOC PHY_CONTROL_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]





set_property LOC PHASER_REF_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]





set_property LOC OLOGIC_X1Y57 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]







set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]

set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]

          







set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]



set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start

set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start



#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20

set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20

set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5

#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]

set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}]

          

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20

          