# クロックのUCF記述 NET "xtalclk_ip" TNM_NET = "xtalclk_ip"; TIMESPEC TS_xtalclk_ip = PERIOD "xtalclk_ip" 20 ns HIGH 50 %; NET "xtalclk_ip" LOC = C11 | IOSTANDARD = LVCMOS33; #NET "xtalclk_ip" CLOCK_DEDICATED_ROUTE = FALSE; #------------------------------------------------------------------------------------- # LEDやプッシュSWのUCF記述 #------------------------------------------------------------------------------------- NET "pushsw_ip" LOC = M2 | IOSTANDARD = LVCMOS33; NET "led_op<0>" LOC = V1 | IOSTANDARD = LVCMOS33; NET "led_op<1>" LOC = U1 | IOSTANDARD = LVCMOS33; NET "led_op<2>" LOC = T1 | IOSTANDARD = LVCMOS33; NET "led_op<3>" LOC = R1 | IOSTANDARD = LVCMOS33; NET "led_op<4>" LOC = N2 | IOSTANDARD = LVCMOS33; NET "led_op<5>" LOC = N1 | IOSTANDARD = LVCMOS33; NET "led_op<6>" LOC = M1 | IOSTANDARD = LVCMOS33; NET "led_op<7>" LOC = L1 | IOSTANDARD = LVCMOS33; #------------------------------------------------------------------------------------- # USB3.0のUCF記述 #------------------------------------------------------------------------------------- NET "fx3_clk_op" LOC = "T11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST"; NET "fx3_flaga_ip" LOC = "U13" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_flagb_ip" LOC = "V12" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_sloe_op" LOC = "T16" | IOSTANDARD = "LVCMOS33" | PULLUP; NET "fx3_slcs_op" LOC = "M16" | IOSTANDARD = "LVCMOS33" | PULLUP; NET "fx3_slwr_op" LOC = "M18" | IOSTANDARD = "LVCMOS33" | PULLUP; NET "fx3_slrd_op" LOC = "U16" | IOSTANDARD = "LVCMOS33" | PULLUP; NET "fx3_pkend_op" LOC = "V11" | IOSTANDARD = "LVCMOS33" | PULLDOWN; NET "fx3_a_op[0]" LOC = "R16" | IOSTANDARD = "LVCMOS33" | PULLDOWN; NET "fx3_a_op[1]" LOC = "M17" | IOSTANDARD = "LVCMOS33" | PULLDOWN; #NET "fx3_reset_ip" LOC = "" | IOSTANDARD = "LVCMOS33" | PULLUP; #NET "fx3_d_bp[*]" IFD_DELAY_VALUE = 0 | IOBDELAY=NONE; NET "fx3_d_bp[0]" LOC = "U17" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[1]" LOC = "V17" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[2]" LOC = "V15" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[3]" LOC = "U18" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[4]" LOC = "U12" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[5]" LOC = "V16" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[6]" LOC = "T18" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[7]" LOC = "U11" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[8]" LOC = "R17" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[9]" LOC = "T14" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[10]" LOC = "R18" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[11]" LOC = "P18" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[12]" LOC = "P17" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[13]" LOC = "N17" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[14]" LOC = "T15" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[15]" LOC = "V14" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[16]" LOC = "L18" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[17]" LOC = "N15" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[18]" LOC = "T9" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[19]" LOC = "M14" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[20]" LOC = "T10" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[21]" LOC = "R10" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[22]" LOC = "L14" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[23]" LOC = "L16" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[24]" LOC = "N16" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[25]" LOC = "M13" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[26]" LOC = "N14" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[27]" LOC = "P15" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[28]" LOC = "U14" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[29]" LOC = "R11" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[30]" LOC = "R15" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; NET "fx3_d_bp[31]" LOC = "P14" | IOSTANDARD = "LVCMOS33" | IOBDELAY=NONE | PULLDOWN; #------------------------------------------------------------------------------------- # GPIOのUCF記述 #------------------------------------------------------------------------------------- #CN2(上側)のピンヘッダ NET "gpio_op[0]" LOC = "V9" | IOSTANDARD = LVCMOS33; NET "gpio_op[1]" LOC = "U8" | IOSTANDARD = LVCMOS33; NET "gpio_op[2]" LOC = "U9" | IOSTANDARD = LVCMOS33; NET "gpio_op[3]" LOC = "U7" | IOSTANDARD = LVCMOS33; NET "gpio_op[4]" LOC = "U6" | IOSTANDARD = LVCMOS33; NET "gpio_op[5]" LOC = "V7" | IOSTANDARD = LVCMOS33; NET "gpio_op[6]" LOC = "V6" | IOSTANDARD = LVCMOS33; NET "gpio_op[7]" LOC = "V5" | IOSTANDARD = LVCMOS33; NET "gpio_op[8]" LOC = "V4" | IOSTANDARD = LVCMOS33; NET "gpio_op[9]" LOC = "U4" | IOSTANDARD = LVCMOS33; NET "gpio_op[10]" LOC = "U3" | IOSTANDARD = LVCMOS33; NET "gpio_op[11]" LOC = "T6" | IOSTANDARD = LVCMOS33; NET "gpio_op[12]" LOC = "R5" | IOSTANDARD = LVCMOS33; NET "gpio_op[13]" LOC = "R7" | IOSTANDARD = LVCMOS33; NET "gpio_op[14]" LOC = "P3" | IOSTANDARD = LVCMOS33; NET "gpio_op[15]" LOC = "P4" | IOSTANDARD = LVCMOS33; NET "gpio_op[16]" LOC = "T4" | IOSTANDARD = LVCMOS33; NET "gpio_op[17]" LOC = "T5" | IOSTANDARD = LVCMOS33; NET "gpio_op[18]" LOC = "V2" | IOSTANDARD = LVCMOS33; NET "gpio_op[19]" LOC = "U2" | IOSTANDARD = LVCMOS33; NET "gpio_op[20]" LOC = "T3" | IOSTANDARD = LVCMOS33; NET "gpio_op[21]" LOC = "R3" | IOSTANDARD = LVCMOS33; NET "gpio_op[22]" LOC = "R2" | IOSTANDARD = LVCMOS33; NET "gpio_op[23]" LOC = "P2" | IOSTANDARD = LVCMOS33; NET "gpio_op[24]" LOC = "N5" | IOSTANDARD = LVCMOS33; NET "gpio_op[25]" LOC = "P5" | IOSTANDARD = LVCMOS33; NET "gpio_op[26]" LOC = "K3" | IOSTANDARD = LVCMOS33; NET "gpio_op[27]" LOC = "L3" | IOSTANDARD = LVCMOS33; #CN1(下側)のピンヘッダ NET "gpio_op[28]" LOC = "F16" | IOSTANDARD = LVCMOS33; NET "gpio_op[29]" LOC = "J18" | IOSTANDARD = LVCMOS33; NET "gpio_op[30]" LOC = "F15" | IOSTANDARD = LVCMOS33; NET "gpio_op[31]" LOC = "J17" | IOSTANDARD = LVCMOS33; NET "gpio_op[32]" LOC = "E17" | IOSTANDARD = LVCMOS33; NET "gpio_op[33]" LOC = "G18" | IOSTANDARD = LVCMOS33; NET "gpio_op[34]" LOC = "D17" | IOSTANDARD = LVCMOS33; NET "gpio_op[35]" LOC = "C17" | IOSTANDARD = LVCMOS33; NET "gpio_op[36]" LOC = "E18" | IOSTANDARD = LVCMOS33; NET "gpio_op[37]" LOC = "C16" | IOSTANDARD = LVCMOS33; NET "gpio_op[38]" LOC = "B18" | IOSTANDARD = LVCMOS33; NET "gpio_op[39]" LOC = "D18" | IOSTANDARD = LVCMOS33; NET "gpio_op[40]" LOC = "A18" | IOSTANDARD = LVCMOS33; NET "gpio_op[41]" LOC = "F18" | IOSTANDARD = LVCMOS33; NET "gpio_op[42]" LOC = "D15" | IOSTANDARD = LVCMOS33; NET "gpio_op[43]" LOC = "C15" | IOSTANDARD = LVCMOS33; NET "gpio_op[44]" LOC = "B16" | IOSTANDARD = LVCMOS33; NET "gpio_op[45]" LOC = "B17" | IOSTANDARD = LVCMOS33; NET "gpio_op[46]" LOC = "A16" | IOSTANDARD = LVCMOS33; NET "gpio_op[47]" LOC = "B14" | IOSTANDARD = LVCMOS33; NET "gpio_op[48]" LOC = "A14" | IOSTANDARD = LVCMOS33; NET "gpio_op[49]" LOC = "A15" | IOSTANDARD = LVCMOS33; NET "gpio_op[50]" LOC = "B13" | IOSTANDARD = LVCMOS33; NET "gpio_op[51]" LOC = "A13" | IOSTANDARD = LVCMOS33; NET "gpio_op[52]" LOC = "C12" | IOSTANDARD = LVCMOS33; NET "gpio_op[53]" LOC = "B12" | IOSTANDARD = LVCMOS33; NET "gpio_op[54]" LOC = "A11" | IOSTANDARD = LVCMOS33; NET "gpio_op[55]" LOC = "B11" | IOSTANDARD = LVCMOS33; NET "gpio_op[56]" LOC = "A9" | IOSTANDARD = LVCMOS33; NET "gpio_op[57]" LOC = "A10" | IOSTANDARD = LVCMOS33; NET "gpio_op[58]" LOC = "B9" | IOSTANDARD = LVCMOS33; NET "gpio_op[59]" LOC = "C9" | IOSTANDARD = LVCMOS33; NET "gpio_op[60]" LOC = "D9" | IOSTANDARD = LVCMOS33; NET "gpio_op[61]" LOC = "D10" | IOSTANDARD = LVCMOS33; NET "gpio_op[62]" LOC = "B8" | IOSTANDARD = LVCMOS33; NET "gpio_op[63]" LOC = "A8" | IOSTANDARD = LVCMOS33; #------------------------------------------------------------------------------------- # DDR3メモリを使うときのUCF記述 #------------------------------------------------------------------------------------- NET "ddr3_dq[0]" LOC = "K1" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L23N_T3_35 NET "ddr3_dq[1]" LOC = "H5" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L24N_T3_35 NET "ddr3_dq[2]" LOC = "J3" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L22P_T3_35 NET "ddr3_dq[3]" LOC = "H6" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L24P_T3_35 NET "ddr3_dq[4]" LOC = "G3" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L20N_T3_35 NET "ddr3_dq[5]" LOC = "G4" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L20P_T3_35 NET "ddr3_dq[6]" LOC = "J2" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L22N_T3_35 NET "ddr3_dq[7]" LOC = "G6" | IOSTANDARD = SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L19P_T3_35 NET "ddr3_addr[14]" LOC = "B1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_35 NET "ddr3_addr[13]" LOC = "D2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_35 NET "ddr3_addr[12]" LOC = "A4" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L8P_T1_AD14P_35 NET "ddr3_addr[11]" LOC = "B6" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L2N_T0_AD12N_35 NET "ddr3_addr[10]" LOC = "F4" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_35 NET "ddr3_addr[9]" LOC = "E2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_35 NET "ddr3_addr[8]" LOC = "A1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_AD7N_35 NET "ddr3_addr[7]" LOC = "F1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L18P_T2_35 NET "ddr3_addr[6]" LOC = "B2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L10N_T1_AD15N_35 NET "ddr3_addr[5]" LOC = "A3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L8N_T1_AD14N_35 NET "ddr3_addr[4]" LOC = "E3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_35 NET "ddr3_addr[3]" LOC = "G2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_35 NET "ddr3_addr[2]" LOC = "C1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L16N_T2_35 NET "ddr3_addr[1]" LOC = "B4" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L7N_T1_AD6N_35 NET "ddr3_addr[0]" LOC = "C2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L16P_T2_35 NET "ddr3_ba[2]" LOC = "C5" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L1N_T0_AD4N_35 NET "ddr3_ba[1]" LOC = "B3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L10P_T1_AD15P_35 NET "ddr3_ba[0]" LOC = "C4" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L7P_T1_AD6P_35 NET "ddr3_ras_n" LOC = "H1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L17P_T2_35 NET "ddr3_cas_n" LOC = "D3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_35 NET "ddr3_we_n" LOC = "D4" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_35 NET "ddr3_reset_n" LOC = "E1" | IOSTANDARD = LVCMOS15 | SLEW = FAST ; # Pad function: IO_L18N_T2_35 NET "ddr3_cke[0]" LOC = "F3" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_35 NET "ddr3_odt[0]" LOC = "H2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_35 NET "ddr3_cs_n[0]" LOC = "G1" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L17N_T2_35 NET "ddr3_dm[0]" LOC = "K2" | IOSTANDARD = SSTL15 | SLEW = FAST ; # Pad function: IO_L23P_T3_35 NET "ddr3_dqs_p[0]" LOC = "J4" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L21P_T3_DQS_35 NET "ddr3_dqs_n[0]" LOC = "H4" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L21N_T3_DQS_35 NET "ddr3_ck_p[0]" LOC = "A6" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_AD5P_35 NET "ddr3_ck_n[0]" LOC = "A5" | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_AD5N_35 NET "calib_done_d" TIG; NET "sys_rst" TIG; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8; ## INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y11; ## INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y10; ## INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y9; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y107; //INST "u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y2; //INST "u_ddr3_infrastructure/gen_mmcm.mmcm_i" LOC=MMCME2_ADV_X1Y2; NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK"; INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE"; INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES"; TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2500 ps; TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6; INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC"; TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;